In the field of MOSFET device manufacturing, it is well known that in order to scale MOSFET devices below 0.05 .mu.m, the short channel effect problem has to be controlled with the use of a Super-Halo doping profile. This is described, for example, in Y. Taur, et al., "CMOS Devices Below 0.1 .mu.m; How High Will Performance Go?", 1997 IEDM Technical Digest, pp. 215-218. The Super-Halo doping consists of a highly non-uniform profile in both the vertical and the lateral directions. This non-uniform doping profile is seen, for example, in FIG. 1A and simulated I.sub.on /I.sub.off characteristics (25.degree. C.) of a 0.05 .mu.m design with .+-.30% channel length tolerances are shown in FIG. 1B. As is shown in FIG. 1A, pockets of high-doped regions are self-aligned to the gate and source/drain regions which help shield the gate-controlled depletion region from penetrating the source and drain fields. Superior short-channel, V.sub.t, control down to very short channel lengths (&lt;0.035 .mu.m) can be achieved with such an idealistic non-uniform doping profile.
To obtain Super-Halo doping profiles in MOSFETs, the thermal budget used to produce the structure, after halo implantation, has to be minimized, i.e., 1000.degree. C., 1 sec. Utilizing a nitride disposable-spacer technique in processing MOSFET devices will result in minimizing the thermal budget used after halo implants. This prior art technique can be summarized as follows: After poly-gate definition and re-oxidation, nitride spacers (about 100 nm) are formed on the sidewalls of the polysilicon. Source, drain and gate implants are then performed followed by the required doping activation and drive-in anneals (1000.degree. C., 5 seconds). The nitride spacers are subsequently removed (hence the name disposable-spacer) and the source and drain extensions (SDE) and the halo implants are performed. In order to activate the halo and SDE implants while minimizing any lateral (and vertical) diffusion, a very short channel anneal cycle (1000.degree. C., 1 sec) is performed. This very short channel anneal cycle preserves the as-implanted abrupt profile of the halo doping obtaining the Super-Halo doping profile described hereinabove.
main problem with the above prior art technique arises from the way in which the nitride spacers are removed when applied to sub-0.05 .mu.m MOSFET devices with very thin gate oxides (.ltoreq.2 nm). The following two methods are currently employed in the prior art for removing nitride spacers: (1) A wet etch, using, for example, hot phosphoric acid; or (2) A dry etch using, for example, a Chemical Down-stream Etch (CDE) technique.
Both of the above etching processes do not exhibit good etch selectivity between nitride and doped oxide or doped silicon. An etch selectivity of 100:1 or greater (nitride to doped oxide or doped silicon) is required to remove the 100 nm nitride spacer without complete removal of the 2 nm oxide that is formed over the source and drain areas. The present etch selectivity of these techniques is in the order of 10:1.
This problem is clearly demonstrated in FIGS. 2 and 3. Specifically, FIG. 2 shows a sketch of a prior art MOSFET structure before spacer etch. The oxide over the source and drain areas is of the same thickness as the gate oxide (.ltoreq.2 nm). This oxide has also been doped during the source/drain implant step. Upon removing the disposable-nitride spacers, the oxide over the source and drain areas are etched and the source/drain areas are attacked resulting in the MOSFET structure (sketch) shown in FIG. 3.
One obvious solution to the above problem is to increase the oxide thickness over the source and drain areas independent of the gate-oxide thickness (e.g., for the removal of 100 nm nitride spacer, greater than 10 nm of oxide is required over the source and drain areas). This may be done by using a thermal oxidation step after the nitride spacer formation to build-up the oxide over the source/drain areas to the required thickness. Unfortunately, such a technique would result in increased dopant diffusion from the source/drain regions to the thermally grown oxide increasing its etch rate to wet or CDE etches.
In view of the drawbacks with prior art MOSFET fabrication methods, there is a continued need to provide new and improved methods of fabricating MOSFET devices with a Super-Halo doping profile that provide excellent device short channel characteristics and enhanced device performance.